This invention relates to semiconductor memory devices, and more particularly to an improved dummy cell layout for an N-channel MOS memory device of the type employing one-transistor memory cells.
MOS random access memory (RAM) devices, widely used in the manufacture of digital equipment such as minicomputers, continue to offer increased speed capabilities and cost advantages. The cost per bit of storage using MOS RAMs goes down as the number of bits or memory cells per package goes up. Successively larger RAMs have been standards in the industry. A RAM containing 4096 bits, for example, is shown in U.S. Pat. No. 3,940,747 issued Feb. 24, 1976 to Kuo and Kitagawa, assigned to Texas Instruments, while 16,384 bit or "16K" RAMs are described in U.S. Pat. Nos. 4,050,061 and 4,081,701, assigned to Texas Instruments, and in articles in Electronics, Feb. 19, 1976, pp. 116-121, and May 13, 1976, pp. 81-86.
As the number of bits in a semiconductor chip is increased, the cell size decreases, and the magnitude of the storage capacitor in each cell of necessity decreases. Also, the number of cells on a digit line in the array of cells increases, so the capacitance of this line increases, and the delay between the time a cell is addressed and a signal reaches the sense amplifier becomes longer, on average. These factors increase the difficulty in sensing the data signal which exists on a digit line. A full logic level difference between a "1" and a "0" in one of these devices may be perhaps 5 volts; however, the difference in voltage between a "1" and a "0" for the data coupled to a column line and reaching the sense amplifier in the center of the memory array from the selected one-transistor cell and dummy cell may be only fifty millivolts or less. Various circuits for sensing these low-level signals have been used. Memory cell layouts with sense amplifiers in the center of each column line are shown in U.S. Pat. No. 3,940,747, and the Electronics articles mentioned above, and in U.S. Pat. No. 3,838,404 to Heeren, as well as in Electronics, Sept. 13, 1973, Vol. 46, No. 19, pp. 116-121, and IEEE Journal of Solid State Circuits, October, 1972, p. 336, by Stein et al. In each of these circuits, dummy cells are connected to the column lines at positions either adjacent the sense amplifiers or adjacent the outer edge of the column line halves. In either case, the difference in delay can be, at worse case, the time for a signal to propogate the entire length of the column line half. This can render the initial sensing ambiguous when dealing with very small signals. Ideally, the two signals should reach the sense nodes of the sense amplifier at the same time for maximum resolution.
It is therefore a principal object of this invention to provide a dummy cell layout for an MOS RAM, and in particular an arrangement which is of high speed operation as well as high sensitivity.